The present invention relates generally to semiconductor memory devices, and in particular, the present invention relates to floating-gate memory cells and their operation.
Electronic information handling or computer systems, whether large machines, microcomputers or small and simple digital processing devices, require memory for storing data and program instructions. Various memory systems have been developed over the years to address the evolving needs of information handling systems. One such memory system includes semiconductor memory devices.
Semiconductor memory devices are rapidly-accessible memory devices. In a semiconductor memory device, the time required for storing and retrieving information generally is independent of the physical location of the information within the memory device. Semiconductor memory devices typically store information in a large array of cells. A group of cells are electrically connected together by a bit line, or data line. An electrical signal is used to program a cell or cells. The electrical signal on the bit line is controlled by a driver circuit. Accordingly, a semiconductor memory device may include several groups of cells, each coupled together with a bit line operated by a driver circuit.
Computer, communication and industrial applications are driving the demand for memory devices in a variety of electronic systems. One important form of semiconductor memory device includes a non-volatile memory made up of floating-gate memory cells called flash memory. Flash memory is often used where regular access to the data stored in the memory device is desired, but where such data is seldom changed. Computer applications use flash memory to store BIOS firmware. Peripheral devices such as printers store fonts and forms on flash memory. Digital cellular and wireless applications consume large quantities of flash memory and are continually pushing for lower voltages and higher densities. Portable applications such as digital cameras, audio recorders, personal digital assistants (PDAs) and test equipment use flash memory cards as a storage medium.
Conventional flash memory cells make use of a floating-gate transistor including a source, a drain, a floating gate and a control gate. In such devices, access operations are carried out by applying biases to each of these terminals. The floating-gate transistors generally include n-channel floating-gate field-effect transistors, but may also include p-channel floating-gate field-effect transistors.
Write operations are often carried out by channel hot-carrier injection. This process induces a flow of electrons between the source and the drain, and accelerates them toward the floating gate in response to a positive bias applied to the control gate. This is termed hot-carrier injection because the electrons possess sufficient kinetic energy to cross the channel-gate oxide barrier and enter the oxide conduction band. Fowler-Nordheim tunneling can also be used to program the memory cell, such as by applying a positive bias to the control gate, grounding one source/drain region and floating the other source/drain region. The positive bias applied to the control gate causes the electrons to be transferred from the grounded source/drain region to the floating gate. Fowler-Nordheim tunneling is an example of cold-carrier injection as the electrons do not possess kinetic energy in excess of the channel-gate oxide barrier. Instead, the electrons are able to surmount this barrier due to the wave nature of the electron.
Read operations generally include sensing a current between the source and the drain, i.e., the MOSFET current, in response to a bias applied to the control gate. Erase operations are generally carried out through Fowler-Nordheim tunneling. This erase process may include electrically floating one source/drain region, grounding or applying a positive bias to the other source/drain region, and applying a negative voltage to the control gate.
Designers are under constant pressure to reduce manufacturing complexity, and thus cost. It has been proposed that using band-to-band tunneling current as a read sensing current, a floating-gate diode can function as a non-volatile memory cell. See, U.S. Pat. No. 5,814,853 titled xe2x80x9cSourceless Floating Gate Memory Device and Method of Storing Dataxe2x80x9d and issued Sep. 29, 1998 to Chen. This floating-gate diode is described in Chen as a non-volatile memory cell having only one p-n junction per cell. Such a device is similar to a floating-gate transistor used in a typical flash memory cell except that the source has been eliminated. Chen, however, describes a read operation utilizing a read gate voltage of xe2x88x927V to produce current differences between a programmed and an un-programmed device sufficient to serve as a basis for memory operation. While typical flash memory devices include circuitry for producing such pumped negative voltages for use in the relatively infrequent operations of writing and erasing a cell, it is generally undesirable to require such pumped negative voltages for use in the relatively frequent operation of reading a cell.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for alternate non-volatile memory cells, apparatus making use of such memory cells, and methods of their operation.
The above-mentioned problems with memory devices and other problems are addressed by the present invention and will be understood by reading and studying the following specification.
Floating-gate memory cells are described herein having a control gate for coupling to a word line, a floating gate, a first source/drain region for coupling to a bit line, and a floating second source/drain region. Such floating-gate memory cells eliminate the need to provide electrical contact to the second source/drain region, thus simplifying the fabrication process and the array architecture. Such memory cells further eliminate the need for a common array source found in conventional floating-gate memory arrays.
Methods of reading such floating-gate memory cells are also provided. The methods described herein facilitate more aggressive scaling of the memory cells and array as the techniques are less sensitive to MOSFET short channel effects than some conventional sensing techniques. Methods described herein include capacitance and forward current sensing techniques.
For one embodiment, the invention includes a floating-gate memory cell. The memory cell includes a gate dielectric layer overlying a substrate having a first conductivity type, a floating gate layer overlying the gate dielectric layer, an intergate dielectric layer overlying the floating gate layer, and a control gate layer overlying the intergate dielectric layer for coupling to a word line. The memory cell further includes a first source/drain region formed in the substrate for coupling to a bit line and having a second conductivity type different than the first conductivity type. The memory cell further includes a second source/drain region formed in the substrate and having the second conductivity type. The second source/drain region is permanently electrically floating.
For another embodiment, the invention includes a floating-gate memory cell. The memory cell includes a gate dielectric layer overlying a substrate having a first conductivity type, a floating gate layer overlying the gate dielectric layer, an intergate dielectric layer overlying the floating gate layer, and a control gate layer overlying the intergate dielectric layer for coupling to a word line. The memory cell further includes a first source/drain region formed in the substrate for coupling to a bit line and having a second conductivity type different than the first conductivity type. The memory cell further includes a second source/drain region formed in the substrate and having the second conductivity type. No contact is formed to the second source/drain region.
For yet another embodiment, the invention includes a floating-gate memory cell. The memory cell includes a gate dielectric layer overlying a substrate having a first conductivity type, a floating gate layer overlying the gate dielectric layer, an intergate dielectric layer overlying the floating gate layer, and a control gate layer overlying the intergate dielectric layer for coupling to a word line. The memory cell further includes a first source/drain region formed in the substrate for coupling to a bit line and a doped region formed in the substrate below and coupled to the first source/drain region. The first source/drain region and the doped region have a second conductivity type different than the first conductivity type and the doped region is offset from a channel region of the memory cell. The memory cell further includes an electrically floating second source/drain region formed in the substrate and having the second conductivity type. For a further embodiment, the doped region utilizes a dopant species different from the first source/drain region to improve the grading of the p-n junction.
For a further embodiment, the invention provides a method of reading a floating-gate memory cell. The method includes applying a bias to a control gate of the floating-gate memory cell and detecting a charge loss on a bit line coupled to a first source/drain region of the memory cell while a second source/drain region of the memory cell is electrically floating. The bias applied to the control gate is greater than a threshold voltage of the memory cell in a first programmed state and less than a threshold voltage of the memory cell in a second programmed state. Furthermore, the charge loss on the bit line is indicative of the programmed state of the memory cell.
For a still further embodiment, the invention provides a method of reading a floating-gate memory cell formed in a substrate. The method includes applying a bias to a control gate of the floating-gate memory cell, applying a forward bias to a bit line coupled to a first source/drain region of the memory cell while a second source/drain region of the memory cell is electrically floating, and detecting a forward current from the memory cell to the substrate. The bias applied to the control gate is greater than a threshold voltage of the memory cell in a first programmed state and less than a threshold voltage of the memory cell in a second programmed state. Furthermore, the level of the forward current is indicative of the programmed state of the memory cell.
The invention further provides methods and apparatus of varying scope.